Executable Requirements: Oppotunities and Impediments Executable Requirements: Opportunities and Impediments

In a top-down, language-based design methodology, requirements can be specified in an executable format, reducing the ambiguity typically encountered with written requirements, and serving as the starting point for the evolution of more detailed requirements and design specifications. As part of the Rapid Prototyping of Application Specific Signal Processors (RASSP) program, a VHDL executable requirement was constructed to capture the interface timing and functional requirements for an embedded processor intended to form images in real-time for a synthetic aperture radar. This paper includes a brief description of the application, then describes the implementation strategy and issues associated with the development of the VHDL executable requirement, emphasizing the importance of the VHDL test bench concept. Anticipated benefits of widespread utilization of VHDL executable requirements are discussed along with potential impediments to adoption. Areas for additional research and development are identified.